The present invention relates generally to a semiconductor device, and more specifically to an electrically rewritable non-volatile memory device.
FIG. 1 shows a memory cell of a conventional electrically rewritable semiconductor memory device, in which a MOS transistor having a floating gate 103 is used for a memory cell. A data rewriting operation can be executed by applying a high level voltage (referred to as a rewriting or program voltage) to one of a control gate 101 and a drain 102 thereof and a low level voltage (0 V) to the other thereof. In more detail, when a high rewriting voltage is applied to the control gate 101 and a low (0 V) voltage is applied to the drain 102, for instance, an already stored or reserved data can be erased. Thereafter, when a rewriting voltage is applied to the drain 102 and a zero voltage is applied to the control gate 101, a new data can be written.
FIG. 2 shows a general configuration of the conventional electrically rewritable semiconductor device composed of the memory cells as shown in FIG. 1. In the drawing, two address input circuits 3 and 4 receive two address signals A0 and A1 inputted through two address input terminals 1 and 2, respectively, and output these address signals A00 and A10 to an address decoder 5, respectively. The address decoder 5 decodes these two address signals A00 and A10 to select any one of address lines X0, X1, X2, and X3 arranged within a memory cell area 16.
A memory cell array is composed of a plurality of sets of two select transistors TR1 and TR2 (each of whose gates is connected in common to an address line) and a cell transistor M (each of whose the control gate is connected in common to the address line). In more detail, in the case of an address line X0 shown in FIG. 2, each gate of the select transistors TR100, TR110, TR120, and TR130 is connected in common to the address line X0; each source of these transistors is connected to each drain of the memory transistors M00, M10, M20 and M30; each source of these memory transistors is grounded; and each control gate of the memory transistors (e.g. M10, M10, M20 and M30) belonging to the same address is connected in common to an erase line Z of a controller 10 via a transistor TR20 turned on in response to an output of the address line X0. Further, each drain of the select transistors (e.g. TR100, TR101, TR102 and TR103) belonging to the same bit position is connected to the same data line (e.g. D01) of the controller 10.
The controller 10 executes write, erase, or read operation to each of the memory cells M00 to M33 in response to a write signals W, erase signal E or read signal R applied to control terminals 11, 12 and 13, respectively. In data write operation, a data represented by D0, D1, D2 and D3 is given to a data input/output circuit 15 through data input/output terminals 6, 7, 8 and 9, and then written in the memory cells M00 to M33 via the controller 10. In data read operation, a data is read in the reverse direction. Further, in data erase and write (i.e. rewrite) operations, a rewrite voltage V.sub.pp is supplied to a terminal 14 of the controller 10.
The data rewrite operation of the above-mentioned conventional memory device will be described hereinbelow. First, when the erase signal E is set to "1", a rewrite voltage V.sub.pp is applied to the erase line Z and a zero voltage is applied to the data lines D01 to D31. Therefore, if the address line X0 is being selected by the address decoder 5, for instance, the rewrite voltage V.sub.pp is applied to each control gate of the memory cells M00 to M30 belonging to the selected address line X0 via the transistor (the select gate) TR20 and the zero voltage is applied to each drain of the memory cells M00 to M30 via the transistor TR100 to TR130, so that data in the memory cells M00 to M30 are erased. Subsequently, when the write signal W is set to "1", a zero voltage is applied to the erase line z; a zero voltage is applied to the data lines D01 to D31 corresponding to "0" level bit positions of an input data D0 to D3 and a rewrite voltage V.sub.pp is applied to the data lines corresponding to "1" level bit positions thereof, so that a data of D0 to D3 can be written in the memory cells M00 to M30 belonging to the same address line X0 selected by the address decoder 5.
As described above, in the conventional electrically data rewritable non-volatile semiconductor memory device, a data is rewritten in such a way that after a data stored in all the memory cells belonging to an address to be rewritten have been erased, irrespective of the logical values thereof, specific logical values (e.g. "1") are written to the memory cells to be written according to the logical values of a data to be written.
In other words, the data erase operation and the data write operation are executed separately or independently. In the prior-art semiconductor memory device, additionally, since the data erasing or writing time duration is as long as several milliseconds as compared with that of other memory devices, there exists a shortcoming in that a long time is required to rewrite a data. Furthermore, since the data erase operation and the data write operation are executed separately, there exists another problem in that the data rewrite processing task is complicated and troublesome. Furthermore, since a rewrite voltage of a relatively high voltage is frequently applied to a memory cell for a long time, there arises another problem in that the memory cells are damaged, thus resulting in a short lifetime of the memory cells.
In the conventional memory devices, erace, rewrite, and read operations are performed by the unit of a bite. That is, when a data is rewritten, as described above, after a data stored in all the memory cells belonging to an address to be rewritten have been erased, irrespective of the logical values thereof, specific logical values (e.g. "1") are written to the memory cells to be written according to the logical values of a bite data to be written.
Accordingly, for memory cells which are not necessary to be read or rewritten in the selected address, read or rewritten operation is performed as well as the objective memory cells.
In such a case, conventionally, a method has been adopted such that all the data stored in all the memory cells belonging to an address line including the memory cells to be read or rewritten are once read and then temporarily stored in an external storage unit, while keeping all the data stored in memory cells other than the above memory cells. In this method, however, when a data stored in any given memory cells at an address is required to be rewritten, the data rewriting operation is complex.
Further, in the electrically rewritable semiconductor memory device, in general the memory cells are damaged whenever the data rewriting operation is executed. Therefore, since all the data stored in all the memory cells belonging to an address are rewritten, in spite of the fact that partial data stored in partial memory cells belonging to an address are required to be rewritten, there exists another problem in that memory cells at which no data rewriting operation is required are damaged, thus resulting in a short lifetime of the memory cells.
Further, in the conventional electrically rewritable non-volatile semiconductor memory device, since these memory cells are arranged in matrix fashion, whenever a data is rewritten in memory cells belonging to an address, a high voltage for data rewriting operation is inevitably applied to other vertical and horizontal lines connected to the address line to be rewritten. Therefore, there arises another problem in that electric charges stored as a memory data in other memory cells connected to the high voltage lines is reduced.
Furthermore, in the non-volatile memory cells, there exists such a tendency that whenever a stored data is read out of the memory cell, an electric charge stored as a memory data in the memory cell to be read decreases. Therefore, when a data is read out of the memory cells at an address, since the same data read operation is to be executed to all the other memory cells belonging to the same address, there exists a problem in that electric charges stored as a memory data in the memory cells at which no data are required to be read are also reduced.